The present disclosure relates generally to the manufacturing of semiconductor devices, and more particularly to a method for using hard masks in patterning one or more layers in a semiconductor device.
The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than those from the previous generation. However, those advances have increased the complexity of processing and manufacturing ICs and, for those advances to be realized, similar developments in IC processing and manufacturing are necessary. For example, an IC is formed by creating one or more devices (e.g., circuit components) on a substrate using a fabrication process. As the geometry of such devices is reduced to the submicron or deep submicron level, the size and shape of different features of the device become critical.
In one example, polysilicon is often used as a gate electrode in a transistor device. As the gate width shrinks to below 100 nanometers, the roughness of the line edges (“line edge roughness”, or LER) of the polysilicon gate structure adversely affects the performance of the transistor device. Specifically, LER can give a polysilicon gate different effective gate lengths, thereby modifying the transistor performance. This modification can result in a degradation in transistor delay time and saturation current (Id).
One solution for reducing LER is to use a SiO2 oxide hard mask when patterning a layer of polysilicon. In a typical process, a polysilicon layer is put down over a silicon substrate, the silicon substrate typically including a plurality of isolation regions, such as a shallow trench isolation (STI) filled with SiO2. After the polysilicon layer is patterned using the oxide hard mask, the hard mask is removed with a hydrofluoric acid (HF) wet etch process adapted for removing SiO2. Since the HF wet etch is adapted for removing SiO2, it also adversely affects the isolation regions, such as forming divots in the STI.
An alternative to the previously described solution is to use a hard mask formed of a nitride, such as SiN or SiON. Therefore, a wet etch process to remove the hard mask after patterning the polysilicon layer, such as H3PO4, will not adversely affect the SiO2 isolation regions. However, the H3PO4 wet etch process has poor selectivity and also etches a portion of the previously patterned polysilicon layer as well as the silicon substrate. As a result, there can be significant gate length variations and other distortions due to the roughened profile of the etched polysilicon layer, especially comparing n-type metal oxide semiconductor (NMOS) to p-type metal oxide semiconductor (PMOS). Also, the etching of the Si substrate may be undesirable for other reasons.
Accordingly, it is desirable to provide an improved system and method for forming a hard mask for patterning a gate electrode or for patterning other polysilicon structures.